RX113_16 datasheet(4/131 Pages) RENESAS

Il numero della parte	RX113

Spiegazioni elettronici	32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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R01DS0216EJ0110 Rev.1.10

Page 4 of 131

Mar 31, 2016

RX113 Group

1. Overview

Communication

functions

Serial peripheral interface

(RSPI)

 1 channel

 Transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI

clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-

synchronous operation (three lines)

 Capable of handling serial transfer as a master or slave

 Data formats

 Choice of LSB-first or MSB-first transfer

The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or

32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each frame

having up to 32 bits)

 Double buffers for both transmission and reception

USB 2.0 host/function

module (USBc)

 USB Device Controller (UDC) and transceiver for USB 2.0 are incorporated.

 Host/function module: 1 port

 Compliant with USB version 2.0

 Transfer speed: Full-speed (12 Mbps), low-speed (1.5 Mbps)

 OTG (ON-The-Go) is supported.

 Isochronous transfer is supported.

 BC (Battery Charger) is supported.

Serial Sound Interface (SSI)

 1 channel

 Capable of duplex communications

 Various serial audio formats supported

 Master/slave function supported

 Programmable word clock or bit clock generation function

 8/16/18/20/22/24/32-bit data formats supported

 On-chip 8-stage FIFO for transmission/reception

 Supports WS continue mode in which the SSIWS signal is not stopped.

LCD controller/driver (LCDC)

 Internal voltage boosting method, capacitor split method, and external resistance division method are

switchable.

 Segment signal output × common signal output: 40 × 4, 36 × 8

12-bit A/D converter (S12ADb)

 1 unit (1 unit × 17 channels)

 12-bit resolution

 Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 32 MHz

 Operating modes

Scan mode (single scan mode, continuous scan mode, and group scan mode)

 Double trigger mode (duplication of A/D conversion data)

 A/D conversion start conditions

A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC

Temperature sensor (TEMPSA)

 1 channel

 The voltage of the temperature is converted into a digital value by the 12-bit A/D converter.

12-bit D/A converter (R12DAA)

 2 channels

 12-bit resolution

 Output voltage: 0.35 to AVCC - 0.47 V

CRC calculator (CRC)

 CRC code generation for arbitrary amounts of data in 8-bit units

 Select any of three generating polynomials:

X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1

 Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.

Comparator B (CMPBa)

 2 channels

 Function to compare the reference voltage and the analog input voltage

 Window comparator operation or standard comparator operation is selectable

Capacitive touch sensing unit (CTSU)

Detection pin: 12 channels (for 100 pins only)

Data operation circuit (DOC)

Comparison, addition, and subtraction of 16-bit data

Unique ID

32-byte ID code for the MCU

Power supply voltages/Operating frequencies

VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 3.6 V: 32 MHz

Supply current

3.6 mA at 32 MHz (typ.)

Operating temperature range

D version:

40 to +85°C, G version: 40 to +105°C

Packages

100-pin LFQFP (PLQP0100KB-A) 14 × 14 mm, 0.50 mm pitch

100-pin TFLGA (PTLG0100JA-A) 7 × 7 mm, 0.65 mm pitch

64-pin LFQFP (PLQP0064KB-A) 10 × 10 mm, 0.50 mm pitch

On-chip debugging system

E1 emulator (FINE interface)

Table 1.1

Outline of Specifications (3/3)

Classification

Module/Function

Description

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