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TP5088WM Scheda tecnica(PDF) 3 Page - National Semiconductor (TI) |
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TP5088WM Scheda tecnica(HTML) 3 Page - National Semiconductor (TI) |
3 / 6 page Connection Diagram Dual-In-Line Package TLH5004 – 2 Top View Order Number TP5088WM or TP5088N See NS Package M14B or N14A Functional Description With the TONE ENABLE pin pulled low the device is in a low power idle mode with the oscillator inhibited and the output transistor turned off Data on inputs D0 – D3 is ig- nored until a rising transition on TONE ENABLE Data meet- ing the timing specifications is latched in the oscillator and output stage are enabled and tone generation begins The decoded data sets the high group and low group program- mable counters to the appropriate divide ratios These counters sequence two ratioed-capacitor DA converters through a series of 28 equal duration steps per sine wave cycle On-chip regulators ensure good stability of tone am- plitudes with variations in supply voltage and temperature The two tones are summed by a mixer amplifier with pre- emphasis applied to the high group tone The output is an NPN emitter-follower requiring the addition of an external load resistor to VSS Table I shows the accuracies of the tone output frequencies and Table II is the Functional Truth Table TABLE I Output Frequency Accuracy Tone Standard Tone Output % Deviation Group DTMF (Hz) Frequency from Standard Low 697 6948 b 032 Group 770 7701 a 002 fL 852 8524 a 003 941 9400 b 011 High 1209 12060 b 024 Group 1336 13317 b 032 fH 1477 14865 a 064 1633 16390 a 037 Pin Descriptions VDD (Pin 1) This is the positive supply to the device refer- enced to VSS The collector of the TONE OUT transistor is also connected to this pin VSS (Pin 5) This is the negative voltage supply All voltages are referenced to this pin OSC IN OSC OUT (Pins 6 and 7) All tone generation tim- ing is derived from the on-chip oscillator circuit A low-cost 3579545 MHz A-cut crystal (NTSC TV color-burst) is need- ed between pins 6 and 7 Load capacitors and a feedback resistor are included on-chip for good start-up and stability The oscillator is stopped when the TONE ENABLE input is pulled to logic low TONE ENABLE Input (Pin 2) This input has an internal pull-up resistor When TONE ENABLE is pulled to logic low the oscillator is inhibited and the tone generators and output transistor are turned off A low to high transition on TONE ENABLE latches in data from D0 – D3 The oscillator starts and tone generation continues until TONE ENABLE is pulled low again MUTE (Pin 8) This output is an open-drain N-channel de- vice that sinks current to VSS when TONE ENABLE is low and no tones are being generated The device turns off when TONE ENABLE is high D0 D1 D2 D3 (Pins 9 10 11 12) These are the inputs for binary-coded data which is latched in on the rising edge of TONE ENABLE Data must meet the timing specifications of Figure 2 At all other times these inputs are ignored and may be multiplexed with other system functions TONE OUT (Pin 14) This output is the open emitter of an NPN transistor the collector of which is connected internal- ly to VDD When an external load resistor is connected from TONE OUT to VSS the output voltage on this pin is the sum of the high and low group tones superimposed on a DC offset When not generating tones this output transistor is turned off to minimize the device idle current SINGLE TONE ENABLE (Pin 3) This input has an internal pull-up resistor When pulled to VSS the device is in single tone mode and only a single tone will be generated at pin 14 (for testing purposes) For normal operation leave this pin open-circuit or pull to VDD GROUP SELECT (Pin 4) This pin is used to select the high group or low group frequency when the device is in single tone mode It has an internal pull-up resistor Leaving this pin open-circuit or pulling it to VDD will generate the high group while pulling to VSS will generate the low group fre- quency at the TONE OUT pin 3 |
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