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IIS328DQ Scheda tecnica(PDF) 11 Page - STMicroelectronics |
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IIS328DQ Scheda tecnica(HTML) 11 Page - STMicroelectronics |
11 / 40 page DocID027250 Rev 3 11/40 IIS328DQ Mechanical and electrical specifications 40 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram (2) 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production. 2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports. 3. When no communication is ongoing, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors. 2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses; in this condition the measurement chain is powered off. 3. Time to obtain valid data after exiting power-down mode. Table 5. SPI slave timing values Symbol Parameter Value (1) Unit Min. Max. tc(SPC) SPI clock cycle 100 ns fc(SPC) SPI clock frequency 10 MHz tsu(CS) CS setup time 6 ns th(CS) CS hold time 8 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time 50 th(SO) SDO output hold time 9 tdis(SO) SDO output disable time 50 |
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