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AK5558VN Scheda tecnica(PDF) 50 Page - Asahi Kasei Microsystems |
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AK5558VN Scheda tecnica(HTML) 50 Page - Asahi Kasei Microsystems |
50 / 70 page [AK5558] 015099850-E-00 2016/03 - 50 - [2] Serial Control Mode In 3-wire serial mode or I 2C mode, PW1-8 bits control the power of AIN1-8 channels independently. AINn channel is powered down when PWn bit = “0” (n=1-8) and AINn channel is in normal operation when PWn bit = “1”. The power-down channel is reset status and outputs all “0”. The channel summation is controlled by MONO1 and MONO2 bits. RSTN bit must be “0” when changing the setting of MONO1, MONO2 and PW1-8 bits. MONO2 bit MONO1 bit Data on Slot (Normal Output & DSD mode) Slot 8 Slot7 Slot6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 0 0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 0 1 All “0” All “0” All “0” All “0” All “0” All “0” (CH5+6 +7+8)/4 (CH1+2 +3+4)/4 1 0 All “0” All “0” All “0” All “0” (CH7+8) /2 (CH5+6) /2 (CH3+4) /2 (CH1+2) /2 1 1 All “0” All “0” All “0” All “0” All “0” All “0” All “0” (CH1+2+ 3+4+5+6 +7+8)/8 Table 17. Slot Data Assign (Serial Control mode, Normal Output & DSD mode) MONO2 bit MONO1 bit Data on Slot (TDM128) Slot 8 Slot7 Slot6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 0 0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 0 1 All “0” All “0” All “0” All “0” TDMIN TDMIN (CH5+6 +7+8)/4 (CH1+2 +3+4)/4 1 0 All “0” All “0” All “0” All “0” (CH7+8) /2 (CH5+6) /2 (CH3+4) /2 (CH1+2) /2 1 1 All “0” All “0” All “0” All “0” TDMIN TDMIN TDMIN (CH1+2+ 3+4+5+6 +7+8)/8 Table 18. Slot Data Assign (Serial Control Mode, TDM128) MONO2 bit MONO1 bit Data on Slot (TDM256 & TDM512) Slot 8 Slot7 Slot6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 0 0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 0 1 TDMIN TDMIN TDMIN TDMIN TDMIN TDMIN (CH5+6 +7+8)/4 (CH1+2 +3+4)/4 1 0 TDMIN TDMIN TDMIN TDMIN (CH7+8) /2 (CH5+6) /2 (CH3+4) /2 (CH1+2) /2 1 1 TDMIN TDMIN TDMIN TDMIN TDMIN TDMIN TDMIN (CH1+2+ 3+4+5+6 +7+8)/8 Table 19. Slot Data Assign (Serial Control Mode, TDM256 & TDM512) |
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