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AK4376AECB Scheda tecnica(PDF) 56 Page - Asahi Kasei Microsystems |
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AK4376AECB Scheda tecnica(HTML) 56 Page - Asahi Kasei Microsystems |
56 / 68 page [AK4376A] 016014206-E-00 2016/11 - 56 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 0 0 0 PMOSC 0 0 0 PMPLL 01H Power Management 2 0 0 PMLDO1N PMLDO1P 0 0 PMCP2 PMCP1 02H Power Management 3 0 0 0 LPMODE 0 0 0 PMDA 03H Power Management 4 0 LVDTM[2:0] CPMODE[1:0] PMHPR PMHPL 04H Output Mode Setting 0 0 VDDTM[3:0] HPRHZ HPLHZ 05H Clock Mode Select 0 CM[1:0] FS[4:0] 06H Digital Filter Select DASD DASL 0 0 T1 0 NGT NGDIS 07H DAC Mono Mixing INVR MDACR RDACR LDACR INVL MDACL RDACL LDACL 08H Reserved 0 0 0 0 0 0 0 0 09H Reserved 0 0 0 0 0 0 0 0 0AH Reserved 0 0 0 0 0 0 0 0 0BH Lch Output Volume OVOLCN 0 0 OVL[4:0] 0CH Rch Output Volume 0 0 0 OVR[4:0] 0DH HP Volume Control 0 0 0 0 HPG[3:0] 0EH PLL CLK Source Select 0 0 T2 0 0 0 PLS[1:0] 0FH PLL Ref CLK Divider 1 PLD[15:8] 10H PLL Ref CLK Divider 2 PLD[7:0] 11H PLL FB CLK Divider 1 PLM[15:8] 12H PLL FB CLK Divider 2 PLM[7:0] 13H DAC CLK Source 0 0 0 0 0 0 DACCKS[1:0] 14H DAC CLK Divider MDIV[7:0] 15H Audio I/F Format DEVICEID[2:0] MS BCKO DIF DL[1:0] 21H CHIP ID 0 T101 T100 0 0 CHIPID[2:0] 24H Mode Control 0 DSMLP 0 T3 0 0 0 0 26H DAC Adjustment1 T11 T10 T9 T8 T7 T6 T5 T4 2AH DAC Adjustment2 T19 T18 T17 T16 T15 T14 T13 T12 Note 76. PDN pin = “L” resets the registers to their default values. Note 77. The bits defined as “0” must contain a “0” value. Note 78. Writing access from 16H to 20H, 22H, 23H, 25H, 27H to 29H and 2BH to FFH is prohibited. |
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