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AK4376AECB Scheda tecnica(PDF) 39 Page - Asahi Kasei Microsystems |
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AK4376AECB Scheda tecnica(HTML) 39 Page - Asahi Kasei Microsystems |
39 / 68 page [AK4376A] 016014206-E-00 2016/11 - 39 - ■ Headphone Amplifier Output (HPL/HPR pins) Headphone amplifiers are operated by positive and negative power that is supplied from internal charge pump circuit. The VEE2 pin output the negative voltage generated by the internal charge pump circuit from CVDD. This charge pump circuit is switched between VDD mode and 1/2VDD mode by the output level of the headphone amplifiers. The headphone amplifier output is single-ended and centered on HPGND (0 V). A capacitor for AC coupling is not necessary. The load resistance is 14.4 Ω (Min.). The output power is 10 mW when 0 dBFS, RL = 32Ω, AVDD = CVDD = 1.8 V and HPG = 4 dB, and it is 25 mW when 0 dBFS, RL = 32Ω, AVDD = 1.8 V and HPG = 0 dB. Ground loop noise cancelling function for headphone amplifier is available by connecting the HPGND pin to the ground of the jack. HPL pin HPR pin HPG[3:0] bits HPGND pin MIX SDATA Lch Data DAC Lch MIX Volume Volume OVL[4:0] bits OVR[4:0] bits MDACL bit, LDACL bit, RDACL bit MDACR bit, LDACR bit, RDACR bit PMHPL bit PMHPR bit HPG[3:0] bits Invert INVL bit Invert INVR bit PMDA bit DAC Rch SDATA Rch Data Figure 15. DAC & Headphone-Amp Block Diagram Table 18. Charge Pump Mode Setting (N/A: Not available) CPMODE1 bit CPMODE0 bit Mode Operation Voltage 0 0 Class-G Operation Mode Automatic Switching (default) 0 1 ±VDD Operation Mode ±VDD 1 0 ±1/2 VDD Operation Mode ±1/2 VDD 1 1 N/A N/A • Class-G Mode Switching Level: VDD → 1/2 VDD: < 1.05 mW at both channels (@ CVDD = 1.8 V, R L = 32Ω) 1/2 VDD → VDD: ≥ 1.05 mW at either channel (@ CVDD = 1.8 V, R L = 32Ω) When the charge pump operation mode is changed to VDD mode from 1/2 VDD mode, an internal counter for holding VDD mode starts (Table 19). The charge pump changes to 1/2 VDD mode if the output signal level is lower than the switching level and 1/2 VDD mode detection time that is set by LVDTM[2:0] bits is passed after VDD mode hold time is finished. |
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