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AK2401 Scheda tecnica(PDF) 73 Page - Asahi Kasei Microsystems

Il numero della parte AK2401
Spiegazioni elettronici  Direct Conversion Transceiver
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Produttore elettronici  AKM [Asahi Kasei Microsystems]
Homepage  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

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[AK2401]
017003093-E-00
2017/3
73
15. Register Definitions
15.1. <0x01~0x03>FRAC
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x01
X
X
X
X
X
X
FRAC[17:16]
R/W
Initial value
0
0
0x02
FRAC[15:8]
R/W
Initial value
0
0
0
0
0
0
0
0
0x03
FRAC[7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
FRAC[17:0]: Numerator Setting of Dividing Number for N-Divider
Set the numerator of dividing number for a frequency synthesizer. This value must be in a range of 0
FRAC
≤ (MOD-1). Delta-sigma modulator is stopped by setting this value “0”, and the N-Divider works as
an integer dividing PLL.
This setting will be valid after writing to the Address 0x08.
15.2. <0x04~0x06>MOD
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x04
X
X
X
X
X
X
MOD[17:16]
R/W
Initial value
0
0
0x05
MOD[15:8]
R/W
Initial value
0
0
0
0
0
0
0
0
0x06
MOD[7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
MOD[17:0]: Denominator Setting of Dividing Number for N-Divider
Set the denominator of dividing number for a PLL synthesizer. This value must be in a range of 2
≤ MOD
≤ 262143. Since it is possible to set a fine frequency with a larger value, normally set it to the maximum
value 262143 (dec).
This setting will be valid after writing to the Address 0x08.
15.3. <0x07~0x08>INT
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x07
X
X
X
X
INT[11:8]
R/W
Initial value
0
0
0
0
0x08
INT[7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
INT[11:0]: Integer Dividing Number Setting for N-Divider
Set an integer dividing number for a PLL synthesizer. This value must be in a range of 35
≤ INT ≤ 4091.
This setting of the address 0x07 will be valid after writing to the address 0x08.
15.4. <0x09>RDIV
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x09
R[7:0]
R/W
Initial value
1
0
0
0
0
0
0
0
R[7:0]: Dividing Setting of Reference Clock
This value must be in a range of 1 (Not Divided)
≤ RDIV ≤ 255 (Divide by 255).
* Do not set R[7:0] bits to
“00000000”.


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