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AK2401 Scheda tecnica(PDF) 50 Page - Asahi Kasei Microsystems

Il numero della parte AK2401
Spiegazioni elettronici  Direct Conversion Transceiver
Download  103 Pages
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Produttore elettronici  AKM [Asahi Kasei Microsystems]
Homepage  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK2401 Scheda tecnica(HTML) 50 Page - Asahi Kasei Microsystems

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[AK2401]
017003093-E-00
2017/3
50
■ Calculation Sequence
The following is a calculation sequence example with an actual setting.
Calculation Example 1) F9 Filter Characteristics
[Coefficient Limits]
Bit Number
Bit
16
DC Gain
Times
3.9529
Max Coefficient
Dec
19113
Total Coefficient
Dec
129529
Absolute Maximum
Total Coefficient
Dec
204505
PFIL_SAT[2:0]
Bin
100 (4-bit)
PFIL_SIFT[2:0]
Bin
000 (No Shift)
Location
6
5
4
3
2
1
-1
-2
-3
-4
-5
-6
-7
-8
-9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36
(1) Input
S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
(2) Coefficient
S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
(3) Multiplier Output
S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
(4) Rounding Output
S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
(5) Accumulator Output
S
R
R
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
(6) Adjust Part
SA SA SA SA S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
(7) Output
S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
S ••• Sign Bit
D
••• Data Bit
E
••• Excess Bit
SA
••• Saturation Bit
0
••• “0” Addition Bit
Integer bit
Fractional bit
▲••• Bit with Max Signal Level
15bits Extension for Multiplication
5bit Extension
for Accumulation
4bit Saturation
“0” addition for 24-bit adjustment
Process
Figure 31. Programmable FIR Filter Calculation Example 1
An example of the F9 filter of the AK2401 is shown here. In this example, a bit adjustment is executed on
the last step to make the total gain of digital filter -0dB (-7dBFS).
(1) Input bit length is (1.21). The maximum input signal level of programmable FIR filter is -13dBFS at
full scale range (Figure 15). Therefore, the maximum signal is at -
3 Fractional bit (▲) in Figure 31.
(2) Coefficient written by register setting. It has (1.15) bit length.
(3) Multiplication result of (1) and (2). Input signal is extended 15 bits for the bit length of the maximum
coefficient.
(4) Round the data off to 21 bits to reduce the circuit size.
(5) Higher 5 bits are extended for accumulation. In this case, there are 2 excess bits although it is
extended 5 bits according to the absolute maximum total coefficient. Since the filter DC gain is 4
times larger (+12dB), the maximum signal bit is shifted 2 bits to the left.
(6) Execute saturation process. In this case, 4-bit saturation process is executed to make the
maximum signal level bit is higher second bit as total gain of the digital filter should be 0dB
(-7dBFS). Bit length becomes 23-bit by executing 4-bit saturation process. Therefore, add
“0” data
to the LSB for 1 bit to make the data 24 bits.
(7) At final output, the decimal point is shifted 1-bit to the left and the data becomes (1.23). It
expresses that the input signal is increased by 6dB, and the digital filter total gain is 0dB (-7dBFS).


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