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AD5531BRU Scheda tecnica(PDF) 1 Page - Analog Devices |
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AD5531BRU Scheda tecnica(HTML) 1 Page - Analog Devices |
1 / 16 page REV. 0 a Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD5530/AD5531 Serial Input, Voltage Output 12-/14-Bit DACs SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. FEATURES Pin-Compatible 12- and 14-Bit DACs Serial Input, Voltage Output Maximum Output Voltage Range of 10 V Data Readback 3-Wire Serial Interface Clear Function to a User-Defined Voltage Power-Down Function Serial Data Output for Daisy-Chaining 16-Lead TSSOP Packages APPLICATIONS Industrial Automation Automatic Test Equipment Process Control General-Purpose Instrumentation GENERAL DESCRIPTION The AD5530 and AD5531 are single 12-/14-bit serial input, voltage output DACs, respectively. They utilize a versatile 3-wire interface that is compatible with SPI ™, QSPI™, MICROWIRE™, and DSP interface standards. Data is presented to the part in the format of a 16-bit serial word. Serial data is available on the SDO pin for daisy-chaining pur- poses. Data readback allows the user to read the contents of the DAC register via the SDO pin. The DAC output is buffered by a gain of 2 amplifier and refer- enced to the potential at DUTGND. LDAC may be used to update the output of the DAC asynchronously. A power-down ( PD) pin allows the DAC to be put into a low power state, and a CLR pin allows the output to be cleared to a user-defined voltage, the potential at DUTGND. The AD5530 and AD5531 are available in 16-lead TSSOP packages. FUNCTIONAL BLOCK DIAGRAM SYNC SCLK GND R R VOUT DUTGND PD SDO VSS VDD RBEN LDAC + – R R REFIN REFAGND DAC REGISTER SDIN SHIFT REGISTER 12-/14-BIT DAC POWER-DOWN CONTROL LOGIC CLR AD5530/AD5531 |
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