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LC35256FM Scheda tecnica(PDF) 6 Page - Sanyo Semicon Device |
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LC35256FM Scheda tecnica(HTML) 6 Page - Sanyo Semicon Device |
6 / 7 page No. 6302-6/7 LC35256FM, FT-55U/70U Notes:1. WE must be held at the high level during the read cycle. 2. Do not apply reverse phase signals to the DOUT pins when those pins are in the output state. 3. The time tWP is the period when both CE and WE are low. It is defined as the time from the fall of WE to the rise of CE or WE, whichever occurs first. 4. The time tCW is the period when both CE and WE are low. It is defined as the time from the fall of CE to the rise of CE or WE, whichever occurs first. 5. The DOUT pins will be in the high-impedance state if any one of the following hold: OE is at the high level, CE is at the high level, or WE is at the low level. 6. The OE pin must be either held high or held low during the write cycle. 7. DOUT has the same phase as the write data during this write cycle. Parameter Symbol Conditions min typ* max Unit Data retention supply voltage VDR VCE ≥ VCC – 0.2 V 2.0 5.5 V Ta ≤ 25°C 0.02 Data retention supply current ICCDR VCC = 3.0 V Ta ≤ 60°C 1.0 µA VCE ≥ VCC – 0.2 V Ta ≤ 70°C 2.0 Ta ≤ 85°C 3.5 Chip enable setup time tCDR 0ns Chip enable hold time tR tRC** ns Note: * Reference values for VCC = 3 V, Ta = 25°C. ** tRC: Read cycle time Data Retention Conditions at Ta = –40 to +85°C Data Retention Waveforms VCC VCCL* VIH VDR VCE GND VCE ≥ VCC – 0.2 V tCDR tR Data retention mode Circuit Design Notes When designing application circuits, always take the following into consideration and design the circuits so that the absolute maximum ratings are never exceeded. • Supply voltage fluctuations • Sample-to-sample variations in the electrical characteristics of the electronic components used, including semiconductor devices, resistors, and capacitors. • Ambient temperature • Variations in the input and clock signals • The application of abnormal pulses Furthermore, be sure to operate this device within the stipulated ranges of all parameters for which an allowable operating range is specified. When CMOS IC input pins are left in the open state, through currents may occur in internal circuits to which intermediate voltage levels are applied, and this can result in incorrect circuit operation. Be sure to handle all unused input pins as specified in the device documentation. Note: * VCCL 5 V operation: 4.5 V |
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