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S-1004NA50I-I6T1U Scheda tecnica(PDF) 10 Page - Seiko Instruments Inc |
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S-1004NA50I-I6T1U Scheda tecnica(HTML) 10 Page - Seiko Instruments Inc |
10 / 42 page BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN S-1004 Series Rev.2.1_01 10 Electrical Characteristics 1. Nch open-drain output product Table 11 (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection voltage*1 −VDET 0.95 V ≤ VDD ≤ 10.0 V 1.0 V ≤ −VDET(S) < 2.2 V −VDET(S) − 0.022 −VDET(S) −VDET(S) + 0.022 V 1 2.2 V ≤ −VDET(S) ≤ 5.0 V −VDET(S) × 0.99 −VDET(S) −VDET(S) × 1.01 V 1 Hysteresis width VHYS − −VDET × 0.03 −VDET × 0.05 −VDET × 0.07 V 1 Current consumption*2 ISS VDD = 10.0 V, VSENSE = −VDET(S) + 1.0 V − 0.50 0.90 μA 2 Operation voltage VDD − 0.95 − 10.0 V 1 Output current IOUT Output transistor Nch VDS*3 = 0.5 V VSENSE = 0.0 V VDD = 0.95 V 0.59 1.00 − mA 3 VDD = 1.2 V 0.73 1.33 − mA 3 VDD = 2.4 V 1.47 2.39 − mA 3 VDD = 4.8 V 1.86 2.50 − mA 3 Leakage current ILEAK Output transistor Nch VDD = 10.0 V, VDS*3 = 10.0 V, VSENSE = 10.0 V − − 0.08 μA 3 Detection voltage temperature coefficient*4 Δ−VDET ΔTa • −VDET Ta = −40°C to +85°C − ±100 ±350 ppm/°C 1 Detection delay time*5 tDET VDD = 5.0 V − 40 − μs 4 Release delay time*6 tRESET VDD = −VDET(S) + 1.0 V, CD = 4.7 nF 10.79 12.69 14.59 ms 4 SENSE pin resistance RSENSE 1.0 V ≤ −VDET(S) < 1.2 V 5.0 19.0 42.0 M Ω 2 1.2 V ≤ −VDET(S) ≤ 5.0 V 6.0 30.0 98.0 M Ω 2 *1. −VDET: Actual detection voltage value, −VDET(S): Set detection voltage value (the center value of the detection voltage range in Table 3 or Table 4) *2. The current flowing through the SENSE pin resistance is not included. *3. VDS: Drain-to-source voltage of the output transistor *4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation. Δ−VDET ΔTa [] mV/°C *1 = −VDET(S) (typ.)[] V *2 × Δ−VDET ΔTa • −VDET [] ppm/°C *3 ÷ 1000 *1. Temperature change of the detection voltage *2. Set detection voltage *3. Detection voltage temperature coefficient *5. The time period from when the pulse voltage of 6.0 V → −VDET(S) − 2.0 V or 0 V is applied to the SENSE pin to when VOUT reaches VDD / 2, after the output pin is pulled up to 5.0 V by the resistance of 470 k Ω. *6. The time period from when the pulse voltage of 0.95 V → 10.0 V is applied to the SENSE pin to when VOUT reaches VDD × 90%, after the output pin is pulled up to VDD by the resistance of 100 kΩ. |
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