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MC74VHCT86ADR2G Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC74VHCT86ADR2G Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 6 page © Semiconductor Components Industries, LLC, 2014 November, 2014 − Rev. 3 1 Publication Order Number: MC74VHCT86A/D MC74VHCT86A Quad 2-Input XOR Gate / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The MC74VHCT86A is an advanced high speed CMOS 2−input Exclusive−OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high−voltage power supply. The MC74VHCT86A input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows it to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. • High Speed: tPD = 4.8 ns (Typ) at VCC = 5 V • Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C • TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Designed for 2 V to 5.5 V Operating Range • Low Noise: VOLP = 0.8 V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300 mA • ESD Performance: HBM > 2000 V; Machine Model > 200 V • These Devices are Pb−Free and are RoHS Compliant LOGIC DIAGRAM Y = A )B 3 Y1 1 A1 2 B1 6 Y2 4 A2 5 B2 8 Y3 9 A3 10 B3 11 Y4 12 A4 13 B4 14−LEAD SOIC D SUFFIX CASE 751A http://onsemi.com 14−LEAD TSSOP DT SUFFIX CASE 948G L L H H L H L H Inputs Output AB L H H L Y FUNCTION TABLE Device Package Shipping ORDERING INFORMATION MC74VHCT86ADR2G SOIC−14 (Pb−Free) 2500 / Tape & Reel MC74VHCT86ADTR2G TSSOP−14 (Pb−Free) PIN CONNECTION AND MARKING DIAGRAM (Top View) 13 14 12 11 10 9 8 2 1 34567 VCC B4 A4 Y4 B3 A3 Y3 A1 B1 Y1 A2 B2 Y2 GND For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. 2500 / Tape & Reel |
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