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8V43FS92432 Scheda tecnica(PDF) 4 Page - Integrated Device Technology |
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8V43FS92432 Scheda tecnica(HTML) 4 Page - Integrated Device Technology |
4 / 27 page 8V43FS92432 DATA SHEET 1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER 4 REVISION 1 10/28/15 34 VCC Power Positive supply for I/O and core. 35 NB Input Pulldown PLL post-divider configuration for output QB. 36 VCC Power Positive supply for I/O and core. 37 GND Power Power supply ground. 38 NA2 Input Pulldown PLL post-divider configuration for output QA. 39 NA1 Input Pullup PLL post-divider configuration for output QA. 40 NA0 Input Pulldown PLL post-divider configuration for output QA. 41 nPLOAD Input Pulldown Selects the programming interface. 42 VCC Power Positive supply for I/O and core. 43 nMR Input Pullup Device master reset. 44 SDA I/O Pullup I2C data. 45 SCL Input Pullup I2C clock. 46 ADR1 Input Pulldown Selectable two bits of the I2C slave address. 47 ADR0 Input Pulldown Selectable two bits of the I2C slave address. 48 P Input Pullup PLL pre-divider configuration. NOTE 1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics table Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 2pF RPULLUP Input Pullup Resistor 75 k RPULLDOWN Input Pulldown Resistor 75 k Table 1. Pin Description Table Number Name Type1 Description |
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