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8V43FS92432 Scheda tecnica(PDF) 2 Page - Integrated Device Technology |
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8V43FS92432 Scheda tecnica(HTML) 2 Page - Integrated Device Technology |
2 / 27 page 8V43FS92432 DATA SHEET 1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER 2 REVISION 1 10/28/15 Block Diagram ÷P OSC PLL ÷NB ÷NA ÷M fREF fVCO fQA fQB REF_CLK XTAL1 XTAL2 REF_SEL TEST_EN SDA SCL ADR[1:0] PLOAD M[9:0] NA[2:0] NB P CLK_STOPx BYPASS MR QA QB LOCK PLL Configuration Registers I2 C Control nPLOAD nMR nBYPASS nCLK_STOP[A:B] Pin Assignment 48-pin, 7mm x 7mm LQFP Package SCL nMR VCC nPLOAD NA0 NA1 NA2 GND ADR0 ADR1 SDA P M2 M4 GND M5 M6 M7 M8 M9 M0 M1 M3 VCC 123456 7 89 10 11 12 24 23 22 21 20 19 18 16 17 15 14 13 37 38 39 40 41 42 43 45 44 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 It is recommended to use an external RC filter for the analog VCC_PLL supply pin. Please see the application section for details. |
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