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9ZXL1530 Scheda tecnica(PDF) 10 Page - Integrated Device Technology |
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9ZXL1530 Scheda tecnica(HTML) 10 Page - Integrated Device Technology |
10 / 19 page 9ZXL1530 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE IDT® 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 10 9ZXL1530 REV D 112015 Test Loads Clock Periods–Differential Outputs with Spread Spectrum Disabled Clock Periods–Differential Outputs with Spread Spectrum Enabled Differential Output Terminations DIF Zo ( Ω)Rs (Ω) 100 33 85 27 Differential Zo, 10 inches LP-HCSL Differential Output 9ZXL Differential Test Loads Rs Rs 2pF 2pF 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock -c2c jitter AbsPer Min -SSC Short-Term Average Min - ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long-Term Average Max +SSC Short-Term Average Max +c2c jitter AbsPer Max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 SSC OFF Center Freq. MHz DIF Measurement Window Units Notes 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock -c2c jitter AbsPer Min -SSC Short-Term Average Min - ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long-Term Average Max +SSC Short-Term Average Max +c2c jitter AbsPer Max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 Notes: 1 Guaranteed by design and characterization, not 100% tested in production. 3 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode 4 Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode Measurement Window Units SSC ON Center Freq. MHz 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/C K410B+ accuracy requirements (+/-100ppm). The 9ZXL1530 itself does not contribute to ppm error. DIF Notes |
Codice articolo simile - 9ZXL1530_15 |
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Descrizione simile - 9ZXL1530_15 |
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