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MC14536BDWG Scheda tecnica(PDF) 10 Page - ON Semiconductor |
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MC14536BDWG Scheda tecnica(HTML) 10 Page - ON Semiconductor |
10 / 15 page MC14536B http://onsemi.com 10 Figure 11. Time Interval Configuration Using an External Clock, Reset, and Output Monostable to Achieve a Pulse Output (Divide−by−4 Configured) NOTE: When Power is first applied to the device with the RESET input going high, DECODE OUT initializes low. Bringing the RESET input low enables the chip’s internal counters. After RESET goes low, the 2n/2 negative transition of the clock input causes DECODE OUT to go high. Since the MONO−IN input is being used, the output becomes monostable. The pulse width of the output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock period) intervals where n = the number of stages selected from the truth table. PULSE GEN. CLOCK 8-BYPASS A B C D RESET SET CLOCK INH MONO-IN OSC INH IN1 VSS DECODE OUT OUT 2 OUT 1 8 16 +V 6 9 10 11 12 2 1 7 15 14 313 5 4 DECODE OUT RESET IN1 POWERUP VDD RX CX *tw ≈ .00247 • RX • CX0.85 tw in msec RX in kW CX in pF *tw |
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