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CAM35C44 Scheda tecnica(PDF) 4 Page - SMSC Corporation |
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CAM35C44 Scheda tecnica(HTML) 4 Page - SMSC Corporation |
4 / 50 page 4 ARCHITECTURE There are six basic architectural components in the CAM35C44: the multihost CPU interface, the IrCC 2.0, a clock generator, configuration registers, power management, and general purpose I/O ( FIGURE 1). The multihost CPU interface is capable of supporting several bus configurations; including, a non-multiplexed ISA-style address and data bus, and a multiplexed address/data bus with selectable read/write command options. The multihost CPU interface includes support for Hitachi and Mitsubishi microcontrollers. The IrCC 2.0 is a multi-protocol serial communications controller that incorporates an ACE 16C550A UART and a Synchronous Communications Engine (SCE). Refer to the SMSC Infrared Communications Controller 2.0 specification for more information. The clock generator provides connections for a 24MHz crystal or an external clock source. The 24MHz clock directly drives the ACE block. An internal PLL is used for data rates above 115.2Kbps. Power management in the CAM35C44 includes various power down modes and an infrared wake-up option. The general purpose I/O interface provides generic I/O programming capabilities. FIGURE 1 - CAM35C44 BLOCK DIAGRAM MULTIHOST CPU INTERFACE SD[7:0]/AD[7:0] SA[1:0]/GPIO[4:3] SA[4:2]/BS[2:0] nCS AEN ASTRB IOCHRDY nNOWS RESET_DRV IRQ DRQ nDACK TC nIOR/RW nIOW/DSTRB CLOCK GEN GENERAL PURPOSE I/O GPIO[2:0] POWER MGMT CONFIGURATION REGISTERS IRCC 2.0 IRRX IRTX IRMODE/IRRX3 POWER RXD/IRRX TXD/IRTX CONTROL DATA ADDRESS X1/CLK1 x2 PWRGD VCC[2:1],VSS[3:1], VIO HS1 HS0 |
Codice articolo simile - CAM35C44 |
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Descrizione simile - CAM35C44 |
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