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8V79S680 Scheda tecnica(PDF) 8 Page - Integrated Device Technology |
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8V79S680 Scheda tecnica(HTML) 8 Page - Integrated Device Technology |
8 / 52 page 8 ©2016 Integrated Device Technology, Inc August 4, 2016 8V79S680 Datasheet Figure 3: DCB Functional Diagram Table 4: DCB Delay Unit at fDCO = 983.04MHz TDCB Delay Unit (ps) DLC NDCB DLC[1:0] Setting Numeric Value 131 00 1 1 262 01 2 2 393 10 3 3 524 11 4 4 Table 5: DCB Divider Configuration Examplesa a. fDCO = 983.04MHz. fIN (MHz) TDCB Delay Unit in ps DLC PDCB MDCB 245.76 131 1 24 96 262 2 24 48 393 3 24 32 524 4 24 24 491.52 131 1 48 96 262 2 48 48 393 3 48 32 524 4 48 24 983.04 131 1 96 96 262 2 96 48 393 3 96 32 524 4 96 24 f IN P DCB ---------------- f DCO M DCB N DCB ---------------------------------------- = f DCO 983MHz 20MHz = DCO 983.04±20MHz ÷MDCB ÷PDCB Digital Hold fIN Delay Unit TDCB 131ps · (1+DLC[1:0]) f1 f2 DCB_CAL DLC[1:0] ÷NDCB |
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