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ADM1034 Scheda tecnica(PDF) 5 Page - Analog Devices |
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ADM1034 Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 40 page ADM1034 Rev. 0 | Page 5 of 40 Parameter Min Typ Max Unit Test Conditions/Comments ANALOG INPUTS (LOCATION, REF) Input Resistance 80 125 160 kΩ AGTL + INPUT (THERM) Input High Level 0.75 × REF V Input Low Level 0.4 V TACHOMETER ACCURACY Fan Speed Measurement Accuracy ±4 % SERIAL BUS TIMING4 Clock Frequency, fSCLK 400 kHz See Figure 2 Glitch Immunity, tSW 50 ns See Figure 2 Bus Free Time, tBUF 1.3 µs See Figure 2 Start Setup Time, tSU:STA 0.6 µs See Figure 2 Start Hold Time, tHD:STA 0.6 µs See Figure 2 Stop Condition Setup Time tSU:STO 0.6 µs See Figure 2 SCL Low Time, tLOW 1.3 µs See Figure 2 SCL High Time, tHIGH 0.6 µs See Figure 2 SCL, SDA Rise Time, tr 1000 ns See Figure 2 SCL, SDA Fall Time, tf 300 ns See Figure 2 Data Setup Time, tSU:DAT 100 ns See Figure 2 Detect Clock Low Timeout, tTIMEOUT 25 35 ms See Note 5 1 Typicals are at TA = 25°C and represent most likely parametric norm. Standby current typ is measured with VCC = 3.3 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 2 Operation at 5.5 V is guaranteed by design, not production tested. 3 Recommend use of 100 kΩ pull-up resistors for all open-drain outputs from the ADM1034. 4 Guaranteed by design, not production tested. 5 SMBus timeout disabled by default. See the section for more information. SMBUS P S tLOW tR tF tHD:STA tHD:DAT tSU:DAT tSU:STA tHD:STA tSU:STO tHIGH SCL PS SDA tBUF Figure 2. Serial Bus Timing Diagram |
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