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MC14046BFG Scheda tecnica(PDF) 4 Page - ON Semiconductor |
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MC14046BFG Scheda tecnica(HTML) 4 Page - ON Semiconductor |
4 / 8 page MC14046B http://onsemi.com 4 Figure 1. Phase Comparators State Diagrams PHASE COMPARATOR 1 Input Stage PCAin XX PCBin 00 01 11 10 PC1out 01 PHASE COMPARATOR 2 Input Stage PCAin XX PCBin PC2out 01 3−State Output Disconnected LD (Lock Detect) 0 0 1 Refer to Waveforms in Figure 3. 00 01 10 11 00 10 01 11 00 01 10 11 Characteristic Using Phase Comparator 1 Using Phase Comparator 2 No signal on input PCAin. VCO in PLL system adjusts to center frequency (f0). VCO in PLL system adjusts to minimum frequency (fmin). Phase angle between PCAin and PCBin. 90 ° at center frequency (f0), approaching 0 _ and 180° at ends of lock range (2fL) Always 0 _ in lock (positive rising edges). Locks on harmonics of center frequency. Yes No Signal input noise rejection. High Low Lock frequency range (2fL). The frequency range of the input signal on which the loop will stay locked if it was initially in lock; 2fL = full VCO frequency range = fmax – fmin. Capture frequency range (2fC). The frequency range of the input signal on which the loop will lock if it was initially out of lock. Depends on low−pass filter characteristics (see Figure 3). fC v fL fC = fL Center frequency (f0). The frequency of VCOout, when VCOin = 1/2 VDD VCO output frequency (f). Note: These equations are intended to be a design guide. Since calculated component values may be in error by as much as a factor of 4, laboratory experimentation may be required for fixed designs. Part to part frequency variation with identical passive components is typically less than ± 20%. Where: 10K v R1 v 1 M 10K v R2 v 1 M 100pF v C1 v .01 mF Figure 2. Design Information + fmin fmin =(VCO input = VSS) R2(C1 + 32 pF) 1 fmax = R1(C1 + 32 pF) 1 (VCO input = VDD) |
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