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MC100LVEL33DR2G Scheda tecnica(PDF) 1 Page - ON Semiconductor

Il numero della parte MC100LVEL33DR2G
Spiegazioni elettronici  3.3 V ECL /4 Divider
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Produttore elettronici  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC100LVEL33DR2G Scheda tecnica(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 6
1
Publication Order Number:
MC100LVEL33/D
MC100LVEL33
3.3 V ECL ÷4 Divider
Description
The MC100LVEL33 is an integrated
÷4 divider. The LVEL is
functionally equivalent to the EL33 and works from a 3.3 V supply.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flops will attain a random state; the
reset allows for the synchronization of multiple LVEL33’s in a system.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
630 ps Typical Propagation Delay
4.0 GHz Typical Maximum Frequency
ESD Protection:
> 4 KV Human Body Model
> 200 V Machine Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC= 0 V
with VEE = −3.0 V to −3.8 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity:
Level 1 for SOIC−8
Level 3 for TSSOP−8
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 130 Devices
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAMS*
KV33
ALYWG
G
SOIC−8 NB
D SUFFIX
CASE 751−07
1
8
TSSOP−8
DT SUFFIX
CASE 948R−02
1
8
1
8
www.onsemi.com
KVL33
ALYW
G
1
8
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package
SOIC−8
TSSOP−8
ORDERING INFORMATION
Device
Package
Shipping†
MC100LVEL33DG
SOIC−8 NB
(Pb-Free)
98 Units / Tube
MC100LVEL33DR2G
2500Tape & Reel
TSSOP−8
(Pb-Free)
MC100LVEL33DTR2G
2500 Tape & Reel
TSSOP−8
(Pb-Free)
MC100LVEL33DTG
100 Units / Tube
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
SOIC−8 NB
(Pb-Free)


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