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MC100EPT25DTR2G Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC100EPT25DTR2G Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC100EPT25 www.onsemi.com 2 1 2 3 45 6 7 8 Q GND VCC Figure 1. 8-Lead Pinout (Top View) and Logic Diagram D NC D VBB VEE LVTTL LVECL/ECL Table 1. PIN DESCRIPTION PIN Q D*, D* Differential ECL Input Pair FUNCTION LVTTL Output VCC VBB Output Reference Voltage Positive Supply GND Ground VEE Negative Supply NC No Connect * Pins will default LOW when left open. (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. EP Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8NB TSSOP−8 DFN−8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in Transistor Count 111 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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