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MC100EP91MNG Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC100EP91MNG Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 10 page MC100EP91 www.onsemi.com 2 D1 D1 D2 Q0 Q1 Q1 VEE D0 Q0 D2 D0 VCC Figure 1. Logic Diagram Q2 Q2 GND VBB Positive Level Input NECL Output R1 R1 R1 R1 R1 R1 R2 R2 R2 Table 1. PIN DESCRIPTION Pin Name I/O Default State Description SOIC QFN 1, 20 3, 4, 12 VCC − − Positive Supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Opera- tion. 10 15, 16 VEE − − Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Opera- tion. 14, 17 19, 20, 23, 24 GND − − Ground. 4, 7 7, 11 VBB − − ECL Reference Voltage Output 2, 5, 8 5, 8, 13 D[0:2] LVPECL, LVDS, LVTTL, LVCMOS, CML, HSTL Input Low Noninverted Differential Inputs [0:2]. Internal 75 kW to GND. 3, 6, 9 6, 9, 14 D[0:2] LVPECL, LVDS, LVTTL,LVCMOS, CML, HSTL Input High Inverted Differential Inputs [0:2]. Internal 75 kW to GND and 75 kW to VCC. When Inputs are Left Open They Default to (VCC − GND) / 2. 19,16,13 2, 22, 18 Q[0:2] NECL Output − Noninverted Differential Outputs [0:2]. Typically Terminated with 50 W to VTT = VCC − 2 V 18,15,12 1, 21, 17 Q[0:2] NECL Output − Inverted Differential Outputs [0:2]. Typically Terminated with 50 W to VTT = VCC − 2 V 11 10 NC − − No Connect. The NC Pin is NOT Electrically Connected to the Die and may Safely be Connected to Any Voltage from VEE to VCC. N/A − EP − Exposed Pad. (Note 1) 1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat−sinking conduit and may only be electrically connected to VEE (not GND). |
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