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MC100LVEP11DTG Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC100LVEP11DTG Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 13 page MC10LVEP11, MC100LVEP11 www.onsemi.com 2 1 2 3 45 6 7 8 D VEE VCC Q0 D Q1 Q1 Q0 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION PIN FUNCTION D*, D** ECL Data Inputs Q0, Q0, Q1, Q1 ECL Data Outputs VCC Positive Supply VEE Negative Supply EP (DFN−8 only) Thermal exposed pad must be connected to a sufficient ther- mal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. *Pins will default to 2/3 VCC when left open. **Pins will default LOW when left open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8NB TSSOP−8 DFN−8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 110 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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