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LM18293N Scheda tecnica(PDF) 2 Page - National Semiconductor (TI) |
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LM18293N Scheda tecnica(HTML) 2 Page - National Semiconductor (TI) |
2 / 6 page Absolute Maximum Ratings If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications Output Drive Supply Voltage (VS) 36V Logic Supply Voltage (VSS) 36V Input Voltage (VI)7V Enable Voltage (VE)7V Peak Output Current (Non-Repetitive t e 5 ms) 2A Junction Temperature (TJ) a 150 C Thermal Resistance Junction to Case (iJC)14 CW Thermal Resistance Junction to Ambient (iJA)80 CW Internal Power Dissipation Internally Limited Operating Temperature Range b 40 Cto a125 C Storage Temperature Range b 65 Cto a150 C Lead Temperature (Solder 10 seconds) 260 C Electrical Characteristics VS e 24V VSS e 5V T e 25 C L e 04V H e 35V each channel unless otherwise noted Symbol Parameter Conditions Typical Tested Limit Design Limit Units (Note 1) (Note 2) VS Main Supply (Pin 8) Maximum Supply Voltage 36 Vmax VSS Logic Supply (Pin 16) Minimum Logic Supply Voltage 45 Vmin Maximum Logic Supply Voltage 36 Vmax IS Total Quiescent VI e LIO e 0VE e H 2 6 mAmax Supply Current VI e HIO e 0VE e H 16 24 mAmax VE e L 4 mAmax ISS Total Quiescent Logic VI e LIO e 0VE e H 44 60 mAmax Supply Current VI e HIO e 0VE e H 16 22 mAmax (pin 16) VE e L 16 24 mAmax VI Input Voltage Min Value of Low b 03 Vmin Max Value of Low 15 Vmax Min Value of High 23 Vmin Max Value of High (VSS s 7) VSS Vmax Max Value of High (VSS l 7) 7 Vmax II Input Current VI e L b 10 m Amax VI e H 30 100 m Amax VE Enable Voltage Min Value of Low b 03 Vmin (Pins 1 9) Max Value of Low 15 Vmax Min Value of High 23 Vmin Max Value of High (VSS s7) VSS Vmax Max Value of High (VSS l7) 7 Vmax IE Enable Current VE e L b 30 b 100 m Amax VE e H g 10 m Amax VCE sat Top Source Saturation Io eb1 amp 14 18 Vmax Voltage VCE sat Bottom Sink Saturation Io e 1 amp 12 18 Vmax Voltage tr Rise Time 10% – 90% Vo 250 ns tf Fall Time 90% – 10% Vo 250 ns ton Turn-On Delay 50% VI to 50% Vo 450 ns toff Turn-Off Delay 50% VI to 50% Vo 200 ns Note 1 Tested limits are guaranteed and 100% production tested Note 2 Design limits are guaranteed (but not 100% production tested) over the full supply and temperature range These limits are not used to calculate outgoing quality levels 2 |
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