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MC10EP52DTR2G Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC10EP52DTR2G Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 11 page MC10EP52, MC100EP52 www.onsemi.com 2 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram 1 2 3 45 6 7 8 Q VEE VCC D Q CLK CLK D D Flip-Flop PIN CLK*, CLK* FUNCTION ECL Clock Inputs D*, D* ECL Data Input Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. Table 1. PIN DESCRIPTION D L H CLK Z Z Q L H Z = LOW to HIGH Transition Table 2. TRUTH TABLE EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8 NB TSSOP−8 DFN8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 155 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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