MC100EP445FAR2G datasheet(10/19 Pages) ONSEMI

Il numero della parte	MC100EP445FAR2G

Spiegazioni elettronici	ECL 8-Bit Serial/Parallel Converter

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MC10EP445, MC100EP445

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10

APPLICATION INFORMATION

The MC10/100EP445 is an integrated 1:8 serial to parallel

converter with two modes of operation selected by

CKSEL (Pin 7). CKSEL HIGH mode only latches data on

the rising edge of the input CLK and CKSEL LOW mode

latches data on both the rising and falling edge of the input

CLK. CKSEL LOW is the open default state. Either of the

two differential input serial data path provided for this

device, SINA and SINB, can be chosen with the SINSEL pin

(pin 25). SINA is the default input path when SINSEL pin

is left floating. Because of internal pull−downs on the input

pins, all input pins will default to logic low when left open.

The two selectable serial data paths can be used for

loop−back testing as well as the bit error testing.

Upon power−up, the internal flip−flops will attain a

random state. To synchronize multiple flip–flops in the

device, the Reset (pin 1) must be asserted. The reset pin will

disable the internal clock signal irrespective of the CKEN

state (CKEN disables the internal clock circuitry). The

device will grab the first stream of data after the falling edge

of RESET

À, followed by the falling edge of CLKÁ, on

second rising edge of CLK

Â in either CKSEL modes. (See

Figure 6)

CLK

RESET

PCLK

RESET

(Asynchronous Reset)

RESET

(Synchronous ENABLE)

Figure 7. Reset Timing Diagram

À

Á

Â

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