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MC10EP05DTG Scheda tecnica(PDF) 2 Page - ON Semiconductor

Il numero della parte MC10EP05DTG
Spiegazioni elettronici  ECL 2?륤nput Differential AND/NAND
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Produttore elettronici  ONSEMI [ON Semiconductor]
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MC10EP05DTG Scheda tecnica(HTML) 2 Page - ON Semiconductor

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MC10EP05, MC100EP05
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2
Figure 1. 8-Lead Pinout (Top View) and Logic
Diagram
1
2
3
45
6
7
8
Q
VEE
VCC
D0
Q
D1
D1
D0
Table 1. PIN DESCRIPTION
Pin
Function
D0*, D1*, D0**, D1**
ECL Data Inputs
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN−8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
* Pins will default LOW when left open.
** Pins will default to VCC/2when left open.
Table 2. TRUTH TABLE
D0
D1
D0
D1
Q
Q
L
L
H
H
L
H
L
H
H
H
L
L
H
L
H
L
L
L
L
H
H
H
H
L
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
37.5 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb-Free Pkg
SOIC−8NB
TSSOP−8
DFN−8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
137 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.


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