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FDG6317NZ Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FDG6317NZ Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 5 page FDG6317NZ Rev B (W) Electrical Characteristics T A = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V ∆BVDSS ∆T J Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C 13 mV/ °C IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 1 µA IGSS Gate–Body Leakage VGS = ± 12 V, V DS = 0 V ± 10 µA IGSS Gate–Body Leakage VGS = ± 4.5 V, V DS = 0 V ± 1 µA On Characteristics (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.6 1.2 1.5 V ∆VGS(th) ∆T J Gate Threshold Voltage Temperature Coefficient ID = –250 µA, Referenced to 25°C –2 mV/ °C RDS(on) Static Drain–Source On–Resistance VGS = 4.5 V, ID = 0.7 A VGS = 2.5 V, ID = 0.6 A VGS = 4.5 V, ID = 0.7 A, TJ=125°C 300 450 390 400 550 560 m Ω ID(on) On–State Drain Current VGS = 4.5 V, VDS = 5 V 1 A gFS Forward Transconductance VDS = 5 V, ID = 0.7 A 1.8 S Dynamic Characteristics Ciss Input Capacitance 66.5 pF Coss Output Capacitance 19 pF Crss Reverse Transfer Capacitance VDS = 10 V, V GS = 0 V, f = 1.0 MHz 10 pF RG Gate Resistance VGS = 15 mV, f = 1.0 MHz 5.8 Ω Switching Characteristics (Note 2) td(on) Turn–On Delay Time 5.5 11 ns tr Turn–On Rise Time 7 15 ns td(off) Turn–Off Delay Time 7.5 15 ns tf Turn–Off Fall Time VDD = 10 V, ID = 1 A, VGS = 4.5 V, RGEN = 6 Ω 2.5 5 ns Qg Total Gate Charge 0.76 1.1 nC Qgs Gate–Source Charge 0.18 nC Qgd Gate–Drain Charge VDS = 10 V, ID = 0.7 A, VGS = 4.5 V 0.20 nC Drain–Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain–Source Diode Forward Current 0.25 A VSD Drain–Source Diode Forward Voltage VGS = 0 V, IS = 0.25 A (Note 2) 0.8 1.2 V trr Diode Reverse Recovery Time 8.3 nS Qrr Diode Reverse Recovery Charge IF = 0.7 A, diF/dt = 100 A/µs 1.2 nC Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user's board design. RθJA = 415°C/W when mounted on a minimum pad . 2. Pulse Test: Pulse Width < 300 µs, Duty Cycle < 2.0% 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. |
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