MC3403, MC3303

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5

CIRCUIT DESCRIPTION

Figure 2. Inverter Pulse Response

20

ms/DIV

The MC3403/3303 is made using four internally

compensated, two−stage operational amplifiers. The first

stage of each consists of differential input device Q24 and

Q22 with input buffer transistors Q25 and Q21 and the

differential to single ended converter Q3 and Q4. The first

stage performs not only the first stage gain function but also

performs the level shifting and Transconductance reduction

functions. By reducing the Transconductance, a smaller

compensation capacitor (only 5.0 pF) can be employed, thus

saving chip area. The Transconductance reduction is

accomplished by splitting the collectors of Q24 and Q22.

Another feature of this input stage is that the input common

mode range can include the negative supply or ground, in

single supply operation, without saturating either the input

devices or the differential to single−ended converter. The

second stage consists of a standard current source load

amplifier stage.

The output stage is unique because it allows the output to

swing to ground in single supply operation and yet does not

exhibit any crossover distortion in split supply operation.

This is possible because Class AB operation is utilized.

Each amplifier is biased from an internal voltage regulator

which has a low temperature coefficient, thus giving each

amplifier good temperature characteristics as well as

excellent power supply rejection.

Figure 3. Sine Wave Response

Figure 4. Open Loop Frequency Response

1.0

10

100

1.0 k

10 k

100 k

1.0 M

f, FREQUENCY (Hz)

-20

0

20

40

60

80

100

120

50

ms/DIV

*Note Class A B output stage produces distortion less sinewave.

Figure 5. Power Bandwidth

Figure 6. Output Swing versus Supply Voltage

f, FREQUENCY (Hz)

1.0 k

10 k

100 k

1.0 M

-5.0

0

5.0

10

15

20

25

30

+15 V

-15 V

10 k

-

+

0

2.0

4.0

6.0

8.0

10

12

14

16

18

20

0

20

30

10