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MC10EP33DTR2 Scheda tecnica(PDF) 7 Page - ON Semiconductor |
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MC10EP33DTR2 Scheda tecnica(HTML) 7 Page - ON Semiconductor |
7 / 12 page MC10EP33, MC100EP33 http://onsemi.com 7 Figure 3. Input Frequency (fin) versus Output Voltage (VOPP) fin, INPUT FREQUENCY (MHz) 5000 4000 3000 2000 1000 0 900 800 700 600 500 400 300 200 100 0 4500 3500 2500 1500 500 V TT = V CC – 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) W Driver Device Receiver Device QD 50 W 50 V TT Q D Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1504 – Metastability and the ECLinPS Family AN1568 – Interfacing Between LVDS and ECL AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8009 – ECLinPS Plus Spice I/O Model Kit AND8020 – Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. |
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