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ES1030QI Scheda tecnica(PDF) 9 Page - Altera Corporation |
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ES1030QI Scheda tecnica(HTML) 9 Page - Altera Corporation |
9 / 14 page ES1030QI of all devices connected to this part has completed. Voltage Levels and Power-On Reset (POR) The internal circuitry of the ES1030QI is functional over the VDD voltage range from 1.71 V to 5.5 V, allowing operation from standard logic voltages from 1.8 V to 5 V. There is an internal initialization time of up to 2.5 ms while the device is preparing for operation. All I/O signals on the ES1030QI are in a high-impedance state during the hardware initialization time. The POR output indicates by transition to HIGH that the sequencer initialization is complete. The sequencer accepts EN inputs before, during, or after internal initialization, and the outputs begin sequencing in the correct order after the initialization is complete. To avoid additional delay on the first OE, the sequencer should be powered up at least 2.5 ms before the first transition on EN. The PGx signal inputs provide internal pull-ups (~100k ohms) to VDD. External pull ups on the PG signals from the regulator should only be needed if there is significant capacitive loading or leakage current on the PG signals. Logic levels are dependent on the VDD for the ES1030QI as shown in the Electrical Characteristics table. The nFAULT_IN and NEXT_IN signals should have external pull ups to VDD. Transitions on the PGx, nFAULT_IN, and NEXT_IN signals are ignored during the initialization period. The OEx and ALL_PG output drive signals are push- pull active drivers after initialization. Therefore, the output logic drive level is the same as the VDD supply to the ES1030QI. Functionality Waveforms WAVEFORM DEFINITIONS FOR FIGURES 5 TO 9 WAVE PIN D0 Pin 20 (EN) D1 Pin 15 (OE1) D2 Pin 14 (OE2) D3 Pin 5 (OE3) D4 Pin 4 (OE4) D5 Pin 12 (PG1) D6 Pin 13 (PG2) D7 Pin 6 (PG3) D8 Pin 7 (PG4) D9 Pin 17 (ALL_PG) D10 Pin 3 (nFAULT_O) Channel 1 (yellow) Pin 8 (ACNTL) 9 www.altera.com/enpirion |
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