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LM1246 Scheda tecnica(PDF) 9 Page - National Semiconductor (TI) |
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LM1246 Scheda tecnica(HTML) 9 Page - National Semiconductor (TI) |
9 / 51 page Typical Performance Characteristics V CC = 5V, TA = 25˚C unless otherwise specified (Continued) SYSTEM INTERFACE SIGNALS The Horizontal and Vertical Blanking and the Clamping input signals are important for proper functionality of the LM1246. Both blanking inputs must be present for OSD synchroniza- tion. In addition, the Horizontal blanking input also assists in setting the proper cathode black level, along with the Clamp- ing pulse. The Vertical blanking input initiates a blanking level at the LM1246 outputs which is programmable from 3 to 127 lines (we recommend at least 10). The start position of the internal Horizontal blanking pulse is programmable from 0 to 64 pixels ahead of the start position of the Hori- zontal flyback input. Both horizontal and vertical blanking can be individually disabled, if desired. Figure 2 and Figure 3 show the case where the Horizontal and Vertical inputs are logic levels. Figure 2 shows the smaller pin 24 voltage superimposed on the horizontal blanking pulse input to the neck board with R H = 4.7k and C 17 = 0.1 µF. Note where the voltage at pin 24 is clamped to about 1V when the pin is sinking current. Figure 3 shows the smaller pin 1 voltage superimposed on the vertical blanking input to the neck board with C 4 jumpered and RV = 4.7k. These component values correspond to the application cir- cuit of Figure 9. Figures 4, 5 show the case where the horizontal and vertical inputs are from deflection. Figure 4 shows the pin 24 voltage which is derived from a horizontal flyback pulse of 35V peak to peak with R H = 8.2K and C17 jumpered. Figure 5 shows the pin 1 voltage which is derived from a vertical flyback pulse of 55V peak to peak with C 4 = 1500 pF and RV = 120k. Figure 6 shows the pin 23 clamp input voltage superimposed on the neck board clamp logic input pulse. R 31 =1kand should be chosen to limit the pin 23 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9. CATHODE RESPONSE Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video risetime is 1.5 ns. The resulting leading edge has a 7.1 ns risetime and a 7.6% overshoot, while the trailing edge has a 7.1 ns risetime and a 6.9% overshoot with an LM2467 driver. ABL GAIN REDUCTION The ABL function reduces the contrast level of the LM1246 as the voltage on pin 22 is lowered from V CC to around 2V. Figure 8 shows the amount of gain reduction as the voltage is lowered from V CC (5.0V) to 2V. The gain reduction is small until V 22 reaches the knee around 3.7V, where the slope increases. Many system designs will require about 3 dB to 5 dB of gain reduction in full beam limiting. Additional attenu- ation is possible, and can be used in special circumstances. However, in this case, video performance such as video linearity and tracking between channels will tend to depart from normal specifications. OSD PHASE LOCKED LOOP The PLL in the LM1246 has a maximum pixels per line setting significantly higher than that of the LM1247. The range for the LM1246 is from 704 to 1152 pixels per line, in increments of 64. The maximum OSD pixel frequency avail- able is 111 MHz. For example, if the horizontal scan rate is 106kHz, 1024 pixels per line would be acceptable to use, since the OSD pixel frequency is: Horizontal Scan Rate X PPL = 106kHz X 1024 = 108.5 MHz 20068508 FIGURE 8. ABL Gain Reduction Curve www.national.com 9 |
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