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UC1584 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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UC1584 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 8 page 4 UC1584 UC2584 UC3584 PIN DESCRIPTIONS BST1: Collector of the boost switch. This is the connection point of the external boost inductor and boost diode. The boost converter generates the bias supply for the UC3584 from the regulated 5V output. BST2: See BST1. BST2 must be connected externally to BST1 pin. CDLY: Delay Set. External CDLY capacitor sets the delay from the time Short Circuit condition is detected and Fault Condition is asserted. COMP: Output of the Voltage Error Amplifier. CT: Connect the Timing Capacitor between CT and GND. FB: Inverting Input of the Voltage Error Amplifier. GND: Analog System Ground. OUT: Output of the floating driver for an external, N-channel MOSFET. PGND: Power Ground. This is the reference node for the boost bias supply regulator. PGND and GND must be connected externally. RT: A Timing Resistor connected between RT and GND sets the discharge current of the timing capacitor. SRC: Source connection of the floating driver to the external switch. SS: Soft Start. An external capacitor is connected between SS and GND to set the duration of the Soft Start cycle. SYNC: Synchronization Pin. The UC3584 is synchronized from the falling edge of the transformer’s secondary winding. Voltage must exceed 1V at minimum input line. VCC: Bias supply of the chip, approximately 15V. This is also the output of the boost regulator. The VCC pin must be decoupled to PGND. VFLT: Positive rail of the floating driver’s bias supply. Decouple to SRC using a high frequency (ceramic) capacitor. VREG: Output of the internal 5V regulated supply. Must be decoupled to GND. Biasing the UC3584 Bias supply for the UC3584 is generated from the main output of the power supply by a boost regulator. The in- ductor, diode and capacitor of the boost converter are ex- ternal components, while the boost switch is internal to the chip. The boost converter operates in a burst mode with a built-in hysteresis of approximately 1V centered at 15V. This is a bang-bang controller and when enabled has a fixed duty cycle of 75%. Undervoltage Detection The UVLO circuit of the UC3584 monitors the voltage on VCC. During power up and power down, the pulse width modulator and the output driver are disabled and OUT is held active low. Operation is enabled when VCC reaches 10.5V. The UVLO circuitry has a built-in hysteresis of 1.7V (10.5V to 8.8V) thus VCC must drop below 8.8V in order to assert UVLO again. Precision Reference An internal precision bandgap reference provides accu- rate voltages to the error amplifier and other control sec- tions of the IC. A buffered 5V regulated voltage is also available for external circuitry on the VREG pin. This pin must be decoupled to the signal GND connection by a good quality high frequency capacitor. Oscillator and Trailing Edge Synchronization The UC3584 is outfitted with a synchronizable oscillator which also generates a ramp signal across the CT capac- itor for the PWM comparator. For easy implementation of the leading edge pulse width modulation technique, the oscillator has an inverted ramp waveform as shown in Fig. 1. The free running oscillator frequency is deter- mined by the timing components, RT and CT, according to the following approximate equations: R D T MAX = − 93 1 17 . . () () f C RC OSC T TT = −× • • 28 2 10 8 09 . . where RT is the timing resistor, its value should be between 1k Ω and 100kΩ, CT is the timing capacitor, DMAX is the desired maximum duty cycle, and fOSC is the free running oscillator frequency. Figure 2 graphically depicts the measured frequency data. APPLICATION INFORMATION |
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