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UC1584 Scheda tecnica(PDF) 5 Page - Texas Instruments |
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UC1584 Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 8 page 5 UC1584 UC2584 UC3584 Edge Modulation During normal operation the oscillator must be synchro- nized to the falling edge of the transformer secondary waveform. Synchronization is achieved by connecting SYNC to the secondary winding via a resistor divider. The resistor divider must be chosen to provide a SYNC pin voltage in excess of 1V at the lowest operating volt- age on the transformer secondary winding. The UC3584 will generate a narrow internal synchronization pulse which will synchronize the oscillator to the switching fre- quency of the main converter. PWM and Output Driver The UC3584 employs leading edge modulation tech- nique to set the required on time of its output. Leading edge modulation is preferred for secondary side regula- tion in multiple output converters to prevent ambiguity in the primary current waveform. In fact, this is the only fea- sible technique to preserve compatibility with primary side peak current mode control. As Fig. 1 depicts the UC3584 utilizes voltage mode con- trol to regulate output voltage. The output pulse width (the on-time of the MOSFET switch) is determined on a cycle-by-cycle basis by comparing the output of the volt- age error amplifier and the ramp waveforms across the timing capacitor. OUT is asserted when the voltage on COMP exceeds the voltage on CT. There are three more conditions which must be satisfied to obtain an active high on the OUT pin. These conditions are: 1. VCC within normal range (UVLO is inactive), 2. No fault condition is detected, 3. CT is discharging. During the fast charging time of the CT capacitor is held low. Ultimately, the output of the PWM circuitry controls the conduction interval of an external N-channel MOSFET switch in the power supply. The UC3584 employs an on-board, floating gate driver circuit to interface to the external switch. An external capacitor connected be- tween VFLT and SRC acts as a floating power supply for V SEC C T OUT COMP INTERNAL SYNC PULSE Figure 1. Trailing edge synchronization, leading edge modulation. APPLICATION INFORMATION (cont.) UDG-99064 1.E+04 1.E+05 1.E+06 1.E+03 1.E+04 1.E+05 TIMING RESISTOR (Ohms) 47pF 100pF 220pF 470pF 1000pF 1200pF 1500pF Figure 2. Oscillator frequency vs. RT with CT as a parameter. |
Codice articolo simile - UC1584_08 |
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Descrizione simile - UC1584_08 |
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