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UC1826 Scheda tecnica(PDF) 8 Page - Texas Instruments |
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UC1826 Scheda tecnica(HTML) 8 Page - Texas Instruments |
8 / 12 page 8 UC1826 UC2826 UC3826 VREF > 4.65V. The block diagram shows that the thresh- olds are set by comparators. By placing an RC divider on the SEQ pin, the enabling of multiple chips can be se- quenced with different RC time constants. Similarly, dif- ferent RC time constants on the ENBL pins can sequence shutdown. The UVLO keeps the output from switching; however the internal reference starts up with VCC less than 8.4V. The KILL input shuts down the switching of the chip. This can be used in conjunction with an overvoltage comparator for overvoltage protec- tion. In order to restart the chip after KILL has been initi- ated, the chip must be powered down and then back up. A pulse on the ENBL pin also accomplishes this without actually removing voltage to the VCC pin. Load Sharing: Load sharing is accomplished similarly to the UC1907 except it has the added constraint of using the sensed current for average current mode control. The sensed current for the UC1826 has an AC component that is amplified and then averaged. The voltage error amplifier represents this average current. The voltage er- ror amplifier output is the current command signal and its voltage represents the average output load current. The ILIM pin programs the upper clamp voltage of this ampli- fier and consequently the maximum load current. A gain of 2 amplifier connected between the voltage error ampli- fier output and the share amplifier input increases the current share resolution and noise margin. The average current is used as an input to a source only load share buffer amplifier. The output of this amplifier is the current share bus. The IC with the highest sensed current will have the highest voltage on the current share bus and consequently act as the master. The 60mV input offset guarantees that the unit sensing the highest load current is chosen as the master. The adjust amplifier is used by the remaining (slave) ICs to adjust their respective references high in order to bal- ance each IC’s load current. The master’s ADJ pin will be at its 1.0V clamp and connected back to the non-inverting voltage error amplifier input through a high value resistor. This requires the user to initially calculate the control voltage with the ADJ pin at 1.0V. VREF can be adjusted 150mV to 300mV which compen- sates for 5% unit to unit reference mismatch and external resistor mismatch. RADJ will typically be 10 to 30 times larger than R1. This also attenuates the overall variation of the ADJ clamp of 1V ±100mV by a factor of 10 to 30, contributing only a 3mV to 10mV additional delta to VREF. Refer to the UC3907 Application Note U-130 for further information on parallel power supply load sharing. Current Control Loop: The current error amplifier (CEA) needs its loop compensated externally. The zero crossing can be calculated with Equation 3. () ( ) 30 1 2 Frequency dB RC INV COMP = • π RINV is the input resistance at the inverting terminal CA– CCOMP is the capacitance between CA– and CAO. Although it is only unity gain stable for a BW of 7MHz, the amplifier is typically configured with a differential gain of at least 10, allowing the amplifier to operate with suffi- cient phase margin at a GBW of 70MHz. A closed loop gain of 10 attenuates the output by 20.8dB 20 8 20 1 11 .log =• to the inverting terminal assuring stability. The amplifier’s gain fed back into the inverting terminal is less than unity at 7MHz, where the phase margin begins to roll off. See Figure 6 for a typical Bode plot. The current error amplifier bandwidth is rolled off and controlled by the voltage error amplifier output. The maxi- mum load current is limited to approximately the maxi- mum voltage across the shunt resistor (maximum of 200mV) divided by RS: () () () 4 I V R MAX LOAD RS S = ILIM sets the maximum current limit by setting the Voh clamp on the voltage error amplifier. If ILIM is not set to limit the Voh to be equal to the maximum voltage across RS, VAO must be attenuated to match the maximum volt- age VRS across the shunt resistor. By attenuating the CIRCUIT BLOCK DESCRIPTION (cont.) β ∅m − Figure 6. Current Error Amplifier Bode Plot |
Codice articolo simile - UC1826_08 |
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Descrizione simile - UC1826_08 |
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