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ST16C2450CP40 Scheda tecnica(PDF) 10 Page - Exar Corporation |
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ST16C2450CP40 Scheda tecnica(HTML) 10 Page - Exar Corporation |
10 / 29 page ST16C2450 áç áç áç áç 2.97V TO 5.5V DUART REV. 4.0.0 10 2.9 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 1 byte FIFO or Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Once the data is received, the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR will generate a receive data ready interrupt upon receiving a character if IER bit-0 has been enabled. 2.9.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the 1 byte receive FIFO that is 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. After the RHR is read, LSR bits 2-4 willl immediately be updated to reflect the errors for the next character byte transferred from the RSR. FIGURE 6. RECEIVER OPERATION Receive Data Shift Register (RSR) Receive Data Byte and Errors RHR Interrupt (ISR bit-2) Receive Data Holding Register (RHR) RXFIFO1 16X Clock Receive Data Characters Data Bit Validation Error Tags in LSR bits 4:2 |
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