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LMZ21701SILR Scheda tecnica(PDF) 3 Page - Texas Instruments |
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LMZ21701SILR Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 37 page TOP SS FB PG VOUT VIN EN VOS GND 1 2 3 4 5 6 7 8 PAD (GND) PAD (GND) LMZ21701 www.ti.com SNVS853D – AUGUST 2012 – REVISED NOVEMBER 2014 6 Pin Configuration and Functions Figure 1. LMZ21701 in the SIL0008E Package SIL0008E 8-Pin Top View Table 1. Pin Functions PIN I/O DESCRIPTION NAME NO. Soft-start pin. An external capacitor connected to this pin sets the internal voltage reference SS 1 I ramp time. It can be used for tracking and sequencing. FB 2 I Voltage feedback. Connect resistive voltage divider to this pin to set the output voltage. Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain PG 3 O (requires pull-up resistor; goes low impedance when EN is low). Output Voltage. Connected to one terminal of the integrated inductor. Connect output filter VOUT 4 O capacitor between VOUT and PGND. GND 5 I Ground for the power MOSFETs and gate-drive circuitry. VOS 6 I Output voltage sense pin and connection for the control loop circuitry. Enable input (High = enabled, Low = disabled). Internal pull down resistor keeps logic level EN 7 I low if pin is left floating. VIN 8 I Supply voltage for control circuitry and power stage. Electrically connected to GND. Must be soldered to a ground copper plane to achieve PAD appropriate power dissipation and mechanical reliability. Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMZ21701 |
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