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TL103WAIDRE4 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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TL103WAIDRE4 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 16 page www.ti.com PACKAGE OUTLINE C TYP -.244 .228 -6.19 5.80 [ ] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] 2X .150 [3.81] TYP -.010 .005 -0.25 0.13 [ ] 0 - 8 -.010 .004 -0.25 0.11 [ ] .010 [0.25] -.050 .016 -1.27 0.41 [ ] .041 [1.04] A NOTE 3 -.197 .189 -5.00 4.81 [ ] B NOTE 4 -.157 .150 -3.98 3.81 [ ] SOIC SOIC - 1.75 mm max height D0008B 4221445/B 04/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B 5 4 PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A TYPICAL DETAIL A SCALE 2.800 9 TL103W, TL103WA www.ti.com SLOS437L – APRIL 2004 – REVISED FEBRUARY 2016 Product Folder Links: TL103W TL103WA Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated |
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