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TL16C2752 Scheda tecnica(PDF) 11 Page - Texas Instruments |
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TL16C2752 Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 26 page BAUD GENERATOR SWITCHING CHARACTERISTICS RECEIVER SWITCHING CHARACTERISTICS (1) TRANSMITTER SWITCHING CHARACTERISTICS TL16C2752 www.ti.com ................................................................................................................................................ SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (for FN package only) LIMITS TEST ALT. PARAMETER FIGURE CONDITION 1.8 V 2.5 V 3.3 V 5 V UNIT SYMBOL S MIN MAX MIN MAX MIN MAX MIN MAX tw3 Pulse duration, BAUDOUT low tLW 6 CLK ÷ 2 50 35 27 16 ns tw4 Pulse duration, BAUDOUT high tHW 6 CLK ÷ 2 50 35 27 16 ns td1 Delay time, XIN ↑ to BAUDOUT↑ tBLD 6 35 25 20 15 ns td2 Delay time, XIN ↑↓ to BAUDOUT↓ tBHD 6 35 25 20 15 ns over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LIMITS ALT. TEST PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX td12 Delay time, RCLK to sample tSCD 9 20 15 10 10 ns Delay time, stop to set INT or 8, 9, 10, RCLK td13 read RBR to LSI interrupt or stop tSINT 1 1 1 1 11, 12 cycle to RXRDY ↓ Delay time, read RBR/LSR to 8, 9, 10, td14 tRINT CL = 30 pF 100 90 80 70 ns reset INT 11, 12 Delay time, RCV threshold byte baudout td26 19 CL = 30 pF 2 to RTS ↑ cycles(2) Delay time, read of last byte in baudout td27 19 CL = 30 pF 2 receive FIFO to RTS ↓ cycles Delay time, first data bit of 16th baudout td28 20 CL = 30 pF 2 character to RTS ↑ cycles Delay time, RBRRD low to RTS ↓ baudout td29 20 CL = 30 pF 2 cycles (1) In the FIFO mode, the read cycle (RC) = 1 baud clock (min) between reads of the receive FIFO and the status registers (interrupt identification register or line status register). (2) A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LIMITS ALT. TEST PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX Delay time, initial write to transmit baudout td15 tIRS 14 8 24 8 24 8 24 8 24 start cycles baudout td16 Delay time, start to INT tSTI 14 8 10 8 10 8 10 8 10 cycles Delay time, IOW (WR THR) to td17 tHR 14 CL = 30 pF 70 60 50 50 ns reset INT Delay time, initial write to INT baudout td18 tSI 14 16 34 16 34 16 34 16 34 (THRE(1)) cycles Delay time, read IOR ↑ to reset INT td19 tIR 14 CL = 30 pF 70 50 35 35 ns (THRE(1)) Delay time, write to TXRDY td20 tWXI 15, 16 CL = 30 pF 60 45 35 35 ns inactive baudout td21 Delay time, start to TXRDY active tSXA 15, 16 CL = 30 pF 9 9 9 9 cycles Setup time, CTS ↑ before midpoint tSU4 18 30 20 10 10 ns of stop bit baudout td25 Delay time, CTS low to TX ↓ 18 CL = 30 pF 24 24 24 24 cycles (1) THRE = Transmitter holding register empty; IIR = interrupt identification register Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TL16C2752 |
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