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TL16C450FN Scheda tecnica(PDF) 6 Page - Texas Instruments

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Il numero della parte TL16C450FN
Spiegazioni elettronici  ASYNCHRONOUS COMMUNICATIONS ELEMENT
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Produttore elettronici  TI1 [Texas Instruments]
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TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VOH‡
HIgh-level output voltage
IOH = − 1 mA
2.4
V
VOL‡
Low-level output voltage
IOL = 1.6 mA
0.4
V
IIkg
Input leakage current
VCC = 5.25 V,
VSS = 0,
±10
A
IIkg
Input leakage current
VCC = 5.25 V,
VSS = 0,
VI = 0 to 5.25 V,
All other terminals floating
±10
µA
IOZ
High-impedance output current
VCC = 5.25 V,
VSS = 0,
VO = 0 V to 5.25 V,
±20
A
IOZ
High-impedance output current
VO = 0 V to 5.25 V,
Chip selected, write mode,or chip deselected
±20
µA
VCC = 5.25 V,
TA = 25°C,
ICC
Supply current
VCC = 5.25 V,
TA = 25 C,
SIN, DSR, DCD, CTS, and RI at 2 V,
10
mA
ICC
Supply current
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V,
Baud rate = 50 kbits/s,
10
mA
CC
All other inputs at 0.8 V,
Baud rate = 50 kbits/s,
XTAL1 at 4 MHz,
No load on outputs
CXTAL1 Clock input capacitance
V
= 0,
V
= 0,
15
20
pF
CXTAL2 Clock output capacitance
VCC = 0,
VSS = 0,
f = 1 MHz,
TA = 25°C,
20
30
pF
Ci
Input capacitance
CC
SS
f = 1 MHz,
TA = 25°C,
All other terminals grounded
6
10
pF
Co
Output capacitance
All other terminals grounded
10
20
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ These parameters apply for all outputs except XTAL2.
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
FIGURE
MIN
MAX
UNIT
tcR
Cycle time, read (tw7 + td8 + td9)
175
ns
tcW
Cycle time, write (tw6 + td5 + td6)
175
ns
tw5
Pulse duration, ADS low
2, 3
15
ns
tw6
Pulse duration, write strobe
2
80
ns
tw7
Pulse duration, read strobe
3
80
ns
twMR
Pulse duration, master reset
1000
ns
tsu1
Setup time, address valid before ADS
2, 3
15
ns
tsu2
Setup time, CS valid before ADS
2, 3
15
ns
tsu3
Setup time, data valid before WR1
↓ or WR2↑
2
15
ns
th1
Hold time, address low after ADS
2, 3
0
ns
th2
Hold time, CS valid after ADS
2, 3
0
ns
th3
Hold time, CS valid after WR1
↑ or WR2↓
2
20
ns
th4§
Hold time, address valid after WR1
↑ or WR2↓
2
20
ns
th5
Hold time, data valid after WR1
↑ or WR2↓
2
15
ns
th6
Hold time, CS valid after RD1
↑ or RD2↓
3
20
ns
th7§
Hold time, address valid after RD1
↑ or RD2↓
3
20
ns
td4§
Delay time, CS valid before WR1
↓ or WR2↑
2
15
ns
td5§
Delay time, address valid before WR1
↓ or WR2↑
2
15
ns
td6
Delay time, write cycle, WR1
↑ or WR2↓ to ADS↓
2
80
ns
td7§
Delay time, CS valid to RD1
↓ or RD2↑
3
15
ns
td8§
Delay time, address valid to RD1
↓ or RD2↑
3
15
ns
td9
Delay time, read cycle, RD1
↑ or RD2↓ to ADS↓
3
80
ns
§ Only applies when ADS is low.


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