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SN74V245-EP Scheda tecnica(PDF) 10 Page - Texas Instruments

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Il numero della parte SN74V245-EP
Spiegazioni elettronici  DSP-SYNC FIRST-IN, FIRST-OUT MEMORY
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SN74V245-EP
SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013
www.ti.com
OUTPUT ENABLE (OE)
When OE is low, the parallel output buffers transmit data from the output register. When OE is high, the Q-output
data bus is in the high-impedance state.
LOAD (LD)
The SN74V245 contains two 12-bit offset registers with data on the inputs, or read on the outputs. When LD is
low and WEN is low, data on the inputs D0–D11 is written into the empty offset register on the first low-to-high
transition of the write clock (WCLK). When LD and WEN are held low, data is written into the full offset register
on the second low-to-high transition of WCLK (see Table 1, Table 2 and Table 3). The third transition of WCLK
again writes to the empty-offset register.
However, writing to all offset registers need not occur at one time. One or two offset registers can be written and
then, by bringing LD high, the FIFO is returned to normal read/write operation. When LD is low, and WEN is low,
the next offset register in sequence is written.
Table 1. Writing to Offset Registers
LD
WEN
WCLK
SELECTION(1)
Writing to offset registers:
L
L
Empty offset
Full offset
L
H
No operation
H
L
Write into FIFO
H
H
No operation
(1)
The same selection sequence applies to reading from the registers.
REN is enabled and read is performed on the low-to-high transition
of RCLK.
Table 2. Empty Offset Register Location and Default Values(1)
17
12 11
0
Empty Offset Register
Not used
Default value
007FH
(1)
Any bits of the offset register not being programmed should be set to zero.
Table 3. Full Offset Register Location and Default Values(1)
17
12 11
0
Full Offset Register
Not used
Default value
007FH
(1)
Any bits of the offset register not being programmed should be set to zero.
When LD is low and WEN is high, the WCLK input is disabled; then, a signal at this input can neither increment
the write-offset-register pointer, nor execute a write.
The contents of the offset registers can be read on the output lines when LD is low and REN is low; then, data
can be read on the low-to-high transition of RCLK. Reading the control registers employs a dedicated read-
offset-register pointer (the read and write pointers operate independently). Offset register content can be read out
in the standard mode only. It is inhibited in the FWFT mode.
A read from and a write to the offset registers should not be performed simultaneously.
FIRST LOAD (FL)
For the single-device mode, see Table 6 for additional information. In the daisy-chain depth-expansion
configuration, FL is grounded to indicate it is the first device loaded and is set high for all other devices in the
daisy chain (see Operating Configurations for further details).
10
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