Motore di ricerca datesheet componenti elettronici |
|
SN74V245-EP Scheda tecnica(PDF) 9 Page - Texas Instruments |
|
|
SN74V245-EP Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 42 page SN74V245-EP www.ti.com SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013 DETAILED DESCRIPTION INPUTS: DATA IN (D0–D17) Data inputs for 18-bit-wide data. CONTROLS: RESET (RS) Reset is accomplished when RS is taken low. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. The half-full flag (HF) and programmable almost-full flag (PAF) is reset to high after tRSF. The programmable almost-empty flag (PAE) is reset to low after tRSF. The full flag (FF) resets to high. The empty flag (EF) resets to low in standard mode, but resets to high in FWFT mode. During reset, the output register is initialized to all zeros, and the offset registers are initialized to their default values. WRITE CLOCK (WCLK) A write cycle is initiated on the low-to-high transition of WCLK. Data setup and hold times must be met with respect to the low-to-high transition of WCLK. The write and read clocks can be asynchronous or coincident. WRITE ENABLE (WEN) When WEN is low, data can be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is high, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow in the standard mode, FF goes low, inhibiting further write operations. Upon completion of a valid read cycle, FF goes high, allowing a write to occur. The FF flag is updated on the rising edge of WCLK. To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. Upon completion of a valid read cycle, IR goes low, allowing a write to occur. The IR flag is updated on the rising edge of WCLK. WEN is ignored when the FIFO is full in either FWFT or standard mode. READ CLOCK (RCLK) Data can be read on the outputs on the low-to-high transition of RCLK when OE is low. The write and read clocks can be asynchronous or coincident. READ ENABLE (REN) When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When REN is high, the output register holds the previous data and no new data is loaded into the output register. Data outputs Q0–Qn maintain the previous data value. In the standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting further read operations. REN is ignored when the FIFO is empty. After a write is performed, EF goes high, allowing a read to occur. The EF flag is updated on the rising edge of RCLK. In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid low-to-high transition of RCLK + tSKEW after the first write. REN need not be asserted low. To access all other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been read from the FIFO, output ready (OR) goes high with a true read (RCLK with REN low), inhibiting further read operations. REN is ignored when the FIFO is empty. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74V245-EP |
Codice articolo simile - SN74V245-EP |
|
Descrizione simile - SN74V245-EP |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |