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LM49250 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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LM49250 Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 36 page LM49250 www.ti.com SNAS406C – JANUARY 2008 – REVISED MAY 2013 Table 1. Bump Description (continued) BUMP NAME DESCRIPTION B2 ADR I2C address select B3 L3D2 Left 3D input B4 L3D1 Left 3D output B5 CCP- Charge pump flying capacitor negative terminal B6 HPR Right ground referenced headphone output C1 GND(LS) Loudspeaker ground C2 I2C_VDD I2C supply voltage C3 R3D2 Right 3D input C4 R3D1 Right 3D output C5 VO(LDO) LDO output voltage C6 HPL Left ground referenced headphone output D1 VDD(LS) Loudspeaker supply voltage D2 SCL I2C clock D3 GND(HP) Headphone ground D4 MIN- Negative mono audio input D5 MIN+ Positive mono audio input D6 LIN- Negative left audio input E1 RLS+ Positive right differential loudspeaker output E2 SDA I2C data E3 RESET I2C reset E4 EP- Negative differential earpiece output E5 RIN+ Positive right audio input E6 LIN+ Positive left audio input F1 RLS- Negative right differential loudspeaker output F2 GND Ground F3 VDD Power supply voltage F4 EP+ Positive differential earpiece output F5 RIN- Negative right audio input F6 BYPASS Amplifier bypass These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM49250 |
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