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74ALVCH16500DGGRG4 Scheda tecnica(PDF) 7 Page - Texas Instruments |
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74ALVCH16500DGGRG4 Scheda tecnica(HTML) 7 Page - Texas Instruments |
7 / 15 page www.ti.com PARAMETER MEASUREMENT INFORMATION VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VOH VOL th tsu From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT S1 Open GND 1 k Ω 1 k Ω Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH − 0.15 V 0 V VCC 0 V 0 V tw VCC VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. 0 V VCC VCC/2 tPHL VCC/2 VCC/2 VCC 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VCC/2 tPLH 2 × VCC VCC SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023I – JULY 1995 – REVISED OCTOBER 2004 V CC = 1.8 V Figure 1. Load Circuit and Voltage Waveforms 7 |
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