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SN74AHC2G126 Scheda tecnica(PDF) 1 Page - Texas Instruments |
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SN74AHC2G126 Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 6 page SN74AHC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCLS440A – SEPTEMBER 1999 – REVISED NOVEMBER 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D EPIC™ (Enhanced-Performance Implanted CMOS) Process D Operating Range 2-V to 5.5-V VCC D Packaged in Plastic Small-Outline Transistor Package description The SN74AHC2G126 is a dual bus buffer gate/line driver with 3-state outputs. The outputs are disabled when the output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The SN74AHC2G126 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE (each gate) INPUTS OUTPUT OE A Y H H H H LL L X Z logic symbol† † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. EN 1 1OE 2 1A 1Y 6 7 2OE 5 2A 2Y 3 1 logic diagram (positive logic) 1A 1Y 1OE 1 26 2A 2OE 7 53 2Y Copyright © 1999, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. DCT PACKAGE (TOP VIEW) 1 2 3 4 8 7 6 5 1OE 1A 2Y GND VCC 2OE 1Y 2A |
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