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SM320F28335-HT Scheda tecnica(PDF) 3 Page - Texas Instruments

Il numero della parte SM320F28335-HT
Spiegazioni elettronici  Digital Signal Controller (DSC)
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SM320F28335-HT Scheda tecnica(HTML) 3 Page - Texas Instruments

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SM320F28335-HT
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SPRS682E – DECEMBER 2010 – REVISED JANUARY 2014
4.7.1
ADC Connections if the ADC Is Not Used
.................................................................. 83
4.7.2
ADC Registers
.................................................................................................. 83
4.7.3
ADC Calibration
................................................................................................. 84
4.8
Multichannel Buffered Serial Port (McBSP) Module
.................................................................. 85
4.9
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
.................................... 88
4.10
Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
.......................................... 93
4.11
Serial Peripheral Interface (SPI) Module (SPI-A)
..................................................................... 96
4.12
Inter-Integrated Circuit (I2C)
............................................................................................. 99
4.13
GPIO MUX
................................................................................................................ 100
4.14
External Interface (XINTF)
.............................................................................................. 107
5
Device Support
................................................................................................................ 109
6
Electrical Specifications
................................................................................................... 109
6.1
Absolute Maximum Ratings
............................................................................................ 109
6.2
Recommended Operating Conditions
................................................................................. 112
6.3
Electrical Characteristics
................................................................................................ 112
6.4
Current Consumption
.................................................................................................... 113
6.4.1
Reducing Current Consumption
............................................................................. 115
6.4.2
Current Consumption Graphs
............................................................................... 116
6.4.3
Thermal Design Considerations
............................................................................. 118
6.5
Emulator Connection Without Signal Buffering for the DSP
....................................................... 118
6.6
Timing Parameter Symbology
.......................................................................................... 120
6.6.1
General Notes on Timing Parameters
...................................................................... 120
6.6.2
Test Load Circuit
.............................................................................................. 120
6.6.3
Device Clock Table
........................................................................................... 120
6.7
Clock Requirements and Characteristics
............................................................................. 122
6.8
Power Sequencing
....................................................................................................... 123
6.8.1
Power Management and Supervisory Circuit Solutions
.................................................. 123
6.9
General-Purpose Input/Output (GPIO)
................................................................................ 126
6.9.1
GPIO - Output Timing
........................................................................................ 126
6.9.2
GPIO - Input Timing
.......................................................................................... 127
6.9.3
Sampling Window Width for Input Signals
................................................................. 128
6.9.4
Low-Power Mode Wakeup Timing
.......................................................................... 129
6.10
Enhanced Control Peripherals
......................................................................................... 133
6.10.1
Enhanced Pulse Width Modulator (ePWM) Timing
....................................................... 133
6.10.2
Trip-Zone Input Timing
....................................................................................... 133
6.11
External Interrupt Timing
................................................................................................ 135
6.12
I2C Electrical Specification and Timing
............................................................................... 136
6.13
Serial Peripheral Interface (SPI) Timing
.............................................................................. 136
6.13.1
Master Mode Timing
.......................................................................................... 136
6.13.2
SPI Slave Mode Timing
...................................................................................... 140
6.14
External Interface (XINTF) Timing
..................................................................................... 143
6.14.1
USEREADY = 0
............................................................................................... 143
6.14.2
Synchronous Mode (USEREADY = 1, READYMODE = 0)
............................................. 144
6.14.3
Asynchronous Mode (USEREADY = 1, READYMODE = 1)
............................................ 144
6.14.4
XINTF Signal Alignment to XCLKOUT
..................................................................... 146
6.14.5
External Interface Read Timing
............................................................................. 147
6.14.6
External Interface Write Timing
............................................................................. 148
6.14.7
External Interface Ready-on-Read Timing With One External Wait State
............................ 150
6.14.8
External Interface Ready-on-Write Timing With One External Wait State
............................. 153
6.14.9
XHOLD and XHOLDA Timing
............................................................................... 156
6.15
On-Chip Analog-to-Digital Converter
.................................................................................. 159
6.15.1
ADC Power-Up Control Bit Timing
.......................................................................... 160
6.15.2
Definitions
...................................................................................................... 161
Copyright © 2010–2014, Texas Instruments Incorporated
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