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LM25069 Scheda tecnica(PDF) 11 Page - Texas Instruments |
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LM25069 Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 29 page LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 If the in-rush limiting condition persists such that the TIMER pin reached 1.72V during t2, the GATE pin is then pulled low by the 2 mA pull-down current. The GATE pin is then held low until either a power up sequence is initiated (LM25069-1), or until the end of the restart sequence (LM25069-2). See the Fault Timer & Restart section. If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 2 mA pull-down current to switch off Q1. Current Limit The current limit threshold is reached when the voltage across the sense resistor RS (VIN to SENSE) reaches 50 mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM25069 resumes normal operation. For proper operation, the RS resistor value should be no larger than 200 mΩ. Higher values may result in instability in the current limit control loop. Circuit Breaker If the load current increases rapidly (e.g., the load is short-circuited) the current in the sense resistor (RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds approximately twice the current limit threshold (95 mV/RS), Q1 is quickly switched off by the 260 mA pull-down current at the GATE pin, and a Fault Timeout Period begins. When the voltage across RS falls below 95 mV the 260 mA pull-down current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 1.72V before the current limiting or power limiting condition ceases, Q1 is switched off by the 2 mA pull-down current at the GATE pin as described in the Fault Timer & Restart section. Power Limit An important feature of the LM25069 is the MOSFET power limiting. The Power Limit function can be used to maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM25069 determines the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current through the sense resistor (VIN to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. Fault Timer & Restart When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is activated, an 80 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 25 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period before the TIMER pin reaches 1.72V, the LM25069 returns to the normal operating mode and CT is discharged by the 2.5 µA current sink. If the TIMER pin reaches 1.72V during the Fault Timeout Period, Q1 is switched off by a 2 mA pull-down current at the GATE pin. The subsequent restart procedure then depends on which version of the LM25069 is in use. The LM25069-1 latches the GATE pin low at the end of the Fault Timeout Period. CT is then discharged to ground by the 2.5 µA fault current sink. The GATE pin is held low by the 2 mA pull-down current until a power up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO pin below its threshold with an open-collector or open-drain device as shown in Figure 24. The voltage at the TIMER pin must be less than 0.3V for the restart procedure to be effective. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM25069 |
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