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SN74ABT7819 Scheda tecnica(PDF) 8 Page - Texas Instruments |
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SN74ABT7819 Scheda tecnica(HTML) 8 Page - Texas Instruments |
8 / 22 page SN54ABT7819 512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS305D – AUGUST 1994 – REVISED APRIL 1998 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION WENA I Port-A write enable. A high level on WENA enables data on A0–A17 to be written into FIFOA–B on the low-to-high transition of CLKA when W/RA is high, CSA is low, and IRA is high. WENB I Port-B write enable. A high level on WENB enables data on B0–B17 to be written into FIFOB–A on the low-to-high transition of CLKB when W/RB is high, CSB is low, and IRB is high. W/RA I Port-A write/read select. A high on W/RA enables A0–A17 data to be written to FIFOA–B on a low-to-high transition of CLKA when WENA is high, CSA is low, and IRA is high. A low on W/RA enables data to be read from FIFOB–A on a low-to-high transition of CLKA when RENA is high, CSA is low, and ORA is high. The A0–A17 outputs are in the high-impedance state when W/RA is high. W/RB I Port-B write/read select. A high on W/RB enables B0–B17 data to be written to FIFOB–A on a low-to-high transition of CLKB when WENB is high, CSB is low, and IRB is high. A low on W/RB enables data to be read from FIFOA–B on a low-to-high transition of CLKB when RENB is high, CSB is low, and ORB is high. The B0–B17 outputs are in the high-impedance state when W/RB is high. AF/AEA HFA ORB IRA RSTA CLKB CLKA 4 3 2 1 2 1 4 3 2 1 Figure 1. Reset Cycle for FIFOA–B† † FIFOB–A is reset in the same manner. |
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