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AD0345AS8500RF Scheda tecnica(PDF) 1 Page - Texas Instruments |
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AD0345AS8500RF Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 61 page SMJ320C6701-SP www.ti.com SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR Check for Samples: SMJ320C6701-SP 1 FEATURES – Bit Counting – Normalization 23456 • Rad-Tolerant: 100-kRad (Si) TID • 1M-Bit On-Chip SRAM • SEL Immune at 89MeV-cm2/mg LET Ions – 512K-Bit Internal Program/Cache (16K 32- • QML-V Qualified, SMD 5962-98661 Bit Instructions) • Highest-Performance Floating-Point Digital – 512K-Bit Dual-Access Internal Data (64K Signal Processor (DSP) SMJ320C6701 Bytes) – 7-ns Instruction Cycle Time • 32-Bit External Memory Interface (EMIF) – 140-MHz Clock Rate – Glueless Interface to Synchronous – Eight 32-Bit Instructions/Cycle Memories: SDRAM and SBSRAM – Up to One GFLOPS Performance – Glueless Interface to Asynchronous – Pin Compatible With ’C6201 Fixed-Point Memories: SRAM and EPROM DSP • Four-Channel Bootloading • SMJ: QML Processing to MIL-PRF-38535 Direct Memory Access (DMA) Controller With • SM: Standard Processing Auxiliary Channel • Operating Temperature Ranges • 16-Bit Host-Port Interface (HPI) – –55°C to 115°C – Access to Entire Memory Map – –55°C to 125°C • Two Multichannel Buffered Serial Ports • VelociTI™ Advanced Very Long Instruction (McBSPs) Word (VLIW) ’C67x CPU Core – Direct Interface to T1/E1, MVIP, SCSA – Eight Highly Independent Functional Units: Framers – Four ALUs (Floating and Fixed Point) – ST Bus Switching Compatible – Two ALUs (Fixed Point) – Up to 256 Channels Each – Two Multipliers (Floating and Fixed – AC97 Compatible Point) – Serial Peripheral Interface (SPI) – Load-Store Architecture With 32 Compatible ( Motorola™) 32-Bit General-Purpose Registers • Two 32-Bit General-Purpose Timers – Instruction Packing Reduces Code Size • Flexible Phase-Locked Loop (PLL) Clock – All Instructions Conditional Generator • Instruction Set Features • IEEE Std 1149.1 (JTAG (1) ) Boundary Scan Compatible – Hardware Support for IEEE Single- Precision Instructions • 429-Pin Ceramic Ball Grid Array (CBGA/GLP) and Ceramic Land Grid Array (CLGA/ZMB) – Hardware Support for IEEE Double- Package Types Precision Instructions • 0.18- μm/5-Level Metal Process – Byte Addressable (8-/16-/32-Bit Data) – CMOS Technology – 32-Bit Address Range • 3.3-V I/Os, 1.9 V Internal – 8-Bit Overflow Protection – Saturation (1) IEEE Std 1149.1-1990 Test Access Port and Boundary Scan – Bit-Field Extract, Set, Clear Architecture 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 VelociTI, XDS, XDS510, XDS510WS are trademarks of Texas Instruments. 3 Windows, Win32, NT are trademarks of Microsoft Corporation. 4 Motorola is a trademark of Motorola, Inc. 5 SPARC is a trademark of SPARC International. 6 Solaris is a trademark of Sun Microsystems, Inc.. PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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